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| upi confidential up1590 1 up1590-ds-p0200, oct. 2013 www.upi-semi.com dual synchronous buck controller with 5v/3.3v 100ma ldos for notebook system power the up1590 is a dual synchronous buck controller with 5v/3.3v 100ma ldos for notebook system power supply solution. the up1590 supports high efficiency, fast transient response and provides a combined pok signal. the ultrasonic mode maintains the switching frequency above audio frequency, which eliminates noise in audio applications. the proprietary rcot tm technology provides fast transient response and high noise immunity. the up1590 has internal soft-start to control the inrush current. other features include over current protection, over/under voltage protection, power-up sequencing, pok output, and thermal shutdown. the up1590 is available in the space saving package wqfn3x3-20l, specified from -40 o c to 85 o c. ? ? ? ? ? wide input voltage range: 5.5v to 26v ? ? ? ? ? two synchronous buck controllers ? ? ? ? ? dual fixed 5v/3.3v outputs or adjusta ble from 2v to 5.5v ? ? ? ? ? selectable dem and usm in light load (up1590p) ? ? ? ? ? internal soft-start and soft-discharge ? ? ? ? ? rcot tm (robust constant on-time) control architecture ? ? ? ? ? 4500ppm/ o c r ds(on) current sensing ? ? ? ? ? 100ma 5v/3.3v ldo with switches ? ? ? ? ? secondary fb input maintains charge pump voltage (up1590q only) ? ? ? ? ? power ok indicator ? ? ? ? ? ovp/uvp/ocp/otp ? ? ? ? ? wqfn3x3-20l ? ? ? ? ? rohs compliant and halogen free rebmunredr oe pytegakca pg nikram po te domnoitarep ok ramer fkqp0951pu l02-3x3nfq w p0951p un ip mneybelbatcele sm ne:31nip fkqq0951p uq 0951p um e db fces:31nip fkqr0951p ur 0951p um s up t:31nip general description applications features ? ? ? ? ? notebook and subnotebook system power supplies ? ? ? ? ? 3-4 cell li-ion battery-power devices ? ? ? ? ? dual output supplies for dsp, memory, logic and microprocessor ordering information note: (1) please check the sample/production availa bility with upi representatives. (2) upi products are compatible with the current ipc/jedec j-std-020 requirements. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes.
upi confidential up1590 2 up1590-ds-p0200, oct. 2013 www.upi-semi.com pin configuration typical application circuit ldo 3 enm ldo 5 en0 vin 19 18 17 16 15 14 13 12 10 9 8 7 4 3 2 1 21 gnd 5 6 11 20 entrip1 entrip2 vfb1 ton vfb2 boot2 pok ugate 2 phase 2 lgate 2 byp1 boot1 ugate1 phase1 lgate1 up1590p up1590p entrip1 entrip2 vfb1 ton vfb2 pokugate2 boot2 phase2 lgate2 ldo3 enm ldo5 en0 vin byp1 boot1 ugate1 phase1 lgate1 21 gnd v in v o1 = 5 v v o2 = 3.3v en0 5v/100ma enm v in pok v reg5 3.3v/100ma v in = 5.5~26v v reg5 19 18 17 16 15 14 13 12 10 9 8 7 4 3 2 1 21 gnd 5 6 11 20 entrip1 entrip2 vfb1 ton vfb2 boot2 pok ugate2 phase2 lgate2 ldo3 secf b ldo5 en0 vin byp1 boot1 ugate1 phase1 lgate1 up1590q 19 18 17 16 15 14 13 12 10 9 8 7 4 3 2 1 21 gnd 5 6 11 20 entrip1 entrip2 vfb1 ton vfb2 boot2 pok ugate 2 phase 2 lgate 2 ldo3 tp ldo5 en0 vin byp1 boot1 ugate1 phase1 lgate1 up1590r upi confidential up1590 3 up1590-ds-p0200, oct. 2013 www.upi-semi.com typical application circuit up1590q entrip1 entrip2 vfb1 ton vfb2 pok ugate2 boot2 phase2 lgate2 ldo3 secfb ldo5 en0 vin byp1 boot1 ugate1 phase1 lgate1 21 gnd v in v o1 = 5 v v o2 = 3.3v en0 5v/100ma v in pok v reg5 3.3v/100ma v in = 5.5~26v v reg5 v o1 v cp up1590r entrip1 entrip2 vfb1 ton vfb2 pok ugate2 boot2 phase2 lgate2 ldo3 tp ldo5 en0 vin byp1 boot1 ugate1 phase1 lgate1 21 gnd v in v o1 = 5 v v o2 = 3.3v en0 5v/100ma v in pok v reg5 3.3v/100ma v in = 5.5~26v v reg5 upi confidential up1590 4 up1590-ds-p0200, oct. 2013 www.upi-semi.com functional block diagram switcher controller pok latch off control on time soft start control entrip2 vfb2 boot2 ugate2 phase2 lgate2 vfb1 entrip1 vin ldo5 en0 byp1 boot1 ugate1 phase1 lgate1 en en ldo3 en 150 o c /140 o c switcher controller enm (up1590p) /secfb (up1590q) /tp (up1590r) gnd ton upi confidential up1590 5 up1590-ds-p0200, oct. 2013 www.upi-semi.com .o ne ma nn oitcnufnip 11 bfv .tupnikcabdeef1kcub r otsisera.reifilpmarorreehtottupnignitrevniehtsinips iht .egatlovrotalugertesotdesusidng ottuptuo morfredivid 21 pirtne .gnittespco dnaelbane1kcub dlohserhttesotdngotnipsihtmorfrotsiseratcennoc r 1kcubsuonorhcnysrof )no(sd o tccvotnipsihttcennocrognitaolfnipsihtevael.pco .1kcubnwodtuhs 3n ot .nip gnittesemit-no ehtrofemit-noehttesotdng otnipsihtmorfrotsiseratcennoc .stefsomreppu 42 pirtne .gnittespco dnaelbane2kcub dlohserhttesotdngotnipsihtmorfrotsiseratcennoc r 2kcubsuonorhcnysrof )no(sd o tccvotnipsihttcennocrognitaolfnipsihtevael.pco .2kcubnwodtuhs 52 bfv .tupnikcabdeef2kcub r otsisera.reifilpmarorreehtottupnignitrevniehtsinips iht .egatlovrotalugertesotdesusidng ottuptuo morfredivid 6k op .noitacidnikorewop egatlovtuptuoehtsetacidnitahterutcetihcraniard-nepo ehtsikop n oitalugernihtiwsiegatlovtuptuoehtnehwecnadepmihgiho ttessinipsiht.tonroydaersi t uptuorehtienehwyletaidem miwoldellupsikop.detanimretsahtiucrictrats-tfosehtd na .noitcetorpronwodtuhs,ybdnats,trats-tfosnisi 72 toob .2kcubforevird etag tefsomreppu gnitaolfehtrofylppus partstoob eht s ihttcennoc.tefsomreppuehtnonrutotegrahcehtsedivorpr oticapacpartstoob .tiucricpartstooba mrofotnip2esahpehtdnanip2toobneewtebroticapacpartst oob 82 etagu .2kcubfotuptuorevird etag tefsomreppu evitpadaehtybderotinom sinipsiht .f fodenrutsahtefsomreppuehtnehw enimretedotyrtiucricnoitcetorphguorht-toohs .tefsomreppufoetagehtotnipsihttcennoc 92 esahp .2kcubfoedon hctiws .r evirdetagtefsomreppuehtrofknisehtsadesusinipsiht e nimretedotyrtiucricnoitcetorphguorht-toohsevitpadae htybderotinom oslasinipsiht t efsomreppuehtfoecruosehtotnipsihttcennoc.ffodenruts ahtefsomreppuehtnehw .tefsomrewolehtfoniardehtdna 0 12 etagl .2kcubfotuptuorevird etag tefsomrewol evitpadaehtybderotinom sinipsiht .f fodenrutsahtefsomrewolehtnehw enimretedotyrtiucricnoitcetorphguorht-toohs .tefsomrewolfoetagehtotnipsihttcennoc 1 1n iv .tupniylppus nivtcennoc.srotalugerodlv3.3dnav5lanretniehtfotupni ehtsinipsiht .tuptuoretpadacaroyrettabehtot 2 10 ne .elbane odl .slennahcrehctiwsnonrutotydaerdnasodlhtobelbane:niv .tiucricllaelbasid:dng 31 mne )p0951pu( .nipnoitcelesedom noitarepo dnatupnielbanexkcub .5odlotnipsihttcennoc:edom cinosartlu .3odlotnipsihttcennoc:edom noitalumeedoid .v8.0evobanipsihthgihllup:elbane bfces )q0951pu( .nipkcabdeefpmupegnahc egrahclanretxelanoitpoehtrotinom otdesusibfceseht .t uptuoehttcetedotdngottuptuopmupegnahcehtmorfredivid evitsiseratcennoc.pmup ehthserferotsruccoeslupcinosartluna,dlohserhtkcabde efstiwolebspord bfcesfi .2etaglro1etaglybnevirdpmupegrahc )r0951pu(pt .niptset .5odlotnipsihteittsum 4 15 odl .odl v5lanretnifotuptuo r oftnerructuptuoam001gnicruosfoelbapacsi5odleht .fu7.4 muminim ahtiwnipsihtssapyb.sdaollanretxe functional pin description upi confidential up1590 6 up1590-ds-p0200, oct. 2013 www.upi-semi.com .o ne ma nn oitcnufnip 5 13 odl .odlv3.3lanretnifotuptuo r oftnerructuptuoam001gnicruosfoelbapacsi3odleht .fu7.4 muminim ahtiwnipsihtssapyb.sdaollanretxe 6 11 etagl .1kcubfotuptuorevird etag tefsomrewol evitpadaehtybderotinom sinipsiht .f fodenrutsahtefsomrewolehtnehw enimretedotyrtiucricnoitcetorphguorht-toohs .tefsomrewolfoetagehtotnipsihttcennoc 7 11 esahp .1kcubfoedon hctiws .r evirdetagtefsomreppuehtrofknisehtsadesusinipsiht e nimretedotyrtiucricnoitcetorphguorht-toohsevitpadae htybderotinom oslasinipsiht t efsomreppuehtfoecruosehtotnipsihttcennoc.ffodenruts ahtefsomreppuehtnehw .tefsomrewolehtfoniardehtdna 8 11 etagu .1kcubfotuptuorevird etag tefsomreppu evitpadaehtybderotinom sinipsiht .f fodenrutsahtefsomreppuehtnehw enimretedotyrtiucricnoitcetorphguorht-toohs .tefsomreppufoetagehtotnipsihttcennoc 9 11 toob .1kcubforevird etag tefsomreppu gnitaolfehtrofylppus partstoob eht s ihttcennoc.tefsomreppuehtnonrutotegrahcehtsedivorpr oticapacpartstoob .tiucricpartstooba mrofotnip1esahpehtdnanip1toobneewtebroticapacpartst oob 0 21 pyb .5odlroftupniegatlovecruosrevo hctiws r ofegatlovylppusot1tuovottcennoc .revohctiwsnehw5odl dapdesopxe .dnuorg otderedlosllewebdluohsdnahtapnoitcudnoctaehsetanimo ddapdesopxeeht .ecnamrofreplamrehtlamitporofbcp functional pin description upi confidential up1590 7 up1590-ds-p0200, oct. 2013 www.upi-semi.com functional description the up1590 implements an unique rcot tm control topology for both synchronous bucks. the up1590 does not require the external compensator. the rcot tm supports extremely low esr output capacitors and makes the design easier and robust. enable and soft start en0 is the control pin of ldo5 and ldo3 regulators. connect this pin to gnd disables two regulators. connect this pin to 3.3v or 5v will turn the two regulators on to standby mode. two smpss become ready to enable at this standby mode. when enm (up1590p) is higher than 0.8v, then both smpss begin to start up. connect this pin to gnd disables two smpss. two smpss operate in diode emulation mode when enm pin voltage is set between 2.3v to 3.6v. if v enm is between 1.2v to 1.8v or between 4.5v to 5v, two smpss operate in ultrasonic mode. the up1590 has an internal 2ms output voltage soft-start for each channel. connect entripx pin to vcc or leave it floating disables the smpsx. for normal operation, connect a resistor from entripx pin to gnd sets over current limit (ocl) threshold. the recommended ocl threshold is from 0.5v to 2.7v. higher or lower threshold beside this recommended range could active the ocl but accuracy may be affected and not preferred. after por, the smpss automatically start up if the entripx is valid (released from the disable state). table 1. enable state 0n em n e1 pirtn e2 pirtn e3 od l5 od l1 hc 2 hc dn gxx x f f of f of fo f fo ni vd n gx xn on of fo f fo ni vh gi hf f of f on on of fo f fo ni vh gi hn of f on on on o f fo ni vh gi hf f on on on of f on o ni vh gi hn on on on on on o table 2. operation mode selection dnem mocer egatlovnip mne edomnoitarepo dn gn wodtuhs v8.1otv2. 1e domcinosartlu v6.3otv3. 2e domnoitalumeedoid v5otv5. 4e domcinosartlu on time control and pwm frequency the up1590 runs with pseudo fixed frequency by feed- forwarding the input and output voltage into the on-time one-shot timer. the on-time is controlled proportional to v out /v in so that the duty ratio will be kept as technically with the same cycle time. the one-shot timer is programmed by a resister r ton connected from ton pin to gnd pin as: n s 20 r v v 10 45 .4 t ton in out 2 v5_ on + = n s 10 r v v 10 5.3 t ton in out 2 v3.3_ on + = the on-time is determined by v in and v out and is kept fairy constant over a wide input and output voltage range at steady state. operation modes (only for up1590p) up1590p supports two operation modes: diode emulation and ultrasonic mode. the operation mode is selected by enm pin. diode emulation mode (enm = ldo3) in diode emulation mode , the up1590 automatically switches over to dem at light load. as the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. the lower mosfet is turned off if detected the negative inductor current. as the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that requires the next on cycle. the frequency is reduced smoothly and hence the power losses is reduced at light load. upi confidential up1590 8 up1590-ds-p0200, oct. 2013 www.upi-semi.com ultrasonic mode (enm = ldo5) ultrasonic mode (usm) is a technique that keeps the switching frequency above audible frequencies while maintaining best of the high conversion efficiency. when the ultrasonic mode is selected, usm control circuit monitors both mosfets and forces to change into the on state if both mosfets are off for more than 32us. usm control circuit detects the over voltage condition and begins to modulate the on-time to keep the output voltage regulated. ldo3/ldo5 linear regulators the up1590 has two sets of 100ma linear regulators which outputs 5v and 3.3v. the ldo5 provides the main power supply for the circuitry of the device and provides the current for gate drivers.the ldo3 is intended mainly for 3.3v supply for the notebook system during standby mode. ldo5 switcher when vout1 finishes soft-start and the voltage higher than its switchover threshold, an internal switch connects byp1 to ldo5 and shuts down the ldo5 simultaneously. when entrip1 goes low, the ldo5 is activated immediately and then internal switch will be off. it decreases the power dissipation from battery. output discharge control when entripx is high, the up1590 discharges outputs using internal mosfet. the current capability of these mosfets is limited to discharge slowly. power ok indicator the up1590 has one pok output indicator. a pull-up resistor is needed for the open-drain output. the pok is actively held low in soft-start, standby, shutdown and protection. it is released when both vo1 and vo2 voltage above than 90% of their nominal regulation voltage and switchover has finished. over current protection the up1590 has cycle-by-cycle over current limiting control. the inductor current is monitored during the off state and the controller keeps the off state when the inductor current is larger than the over current trip level. in order to provide both good accuracy and cost effective solution, up1590 supports temperature compensated mosfet r ds(on) sensing. entripx pin should be connected to gnd through the trip voltage setting resistor, r trip . entripx terminal sources i trip current, which is 10 ua typically at room temperature, and the trip level is set to the ocl trip voltage v trip as below. note that the v trip is limited up to about 270 mv(typ.) internally. functional description ) on ( ds ocp trip trip trip r i 10 ) ua ( i) k( r ) mv ( v = = ) ua ( i 1 0 r i ) k( r trip ) on ( ds ocp trip = the voltage between gnd pin and phasex pin monitors the inductor current so that phasex pin should be connected to the drain terminal of the lower mosfet properly. i trip has 4500 ppm/ o c temperature slope to compensate the temperature dependency of the lower r ds(on) . gnd is used as the positive current sensing node so that gnd should be connected to the proper current sensing device, i.e. the source terminal of the lower mosfet. when the comparison is done during the off state, v trip sets valley level of the inductor current. therefore, the load current at over current threshold, i lim , can be calculated as follows: in out out in dson trip ripple dson trip lim v v ) v v( f l 2 1 r v 2 i r v i + = + = in an over current condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. eventually, it ends up with crossing the under voltage protection threshold and shutdown both channels. over/under voltage protection the up1590 monitors the feedback voltage to detect over and under voltage. when the feedback voltage becomes higher than 112% target voltage, the ovp circuit latches as the upper mos off and the lower mos on. when the feedback voltage becomes lower than 58% target voltage, the uvp occurs and after 10us uvp delay, the up1590 latches off both mosfets, and shuts off both drivers of another channel. this function is enabled after 5ms following entripx has become high. uvlo protection up1590 has ldo5 under voltage lock out protection (uvlo). when the ldo5 voltage is lower than uvlo threshold voltage, both smps are turned off. this is a non- latch protection. upi confidential up1590 9 up1590-ds-p0200, oct. 2013 www.upi-semi.com over temperature protection the up1590 monitors the temperature of itself. if the temperature exceeds typical 150 o c, the up1590 is turned off including ldos. this is a non-latch protection. charge pump (secfb) as shown in the figure1, the external charge pump is driven by lgatex. the total charge pump voltage, v cp , is : d lgatex cp v 4 v 2 vox v + = where v lgatex is the peak voltage of the lgatex driver which is equal to ldo5 and v d is the forward voltage dropped across the schottky diode. the secfb pin in the up1590q is used to monitor the charge pump via a resistive voltage divider to generate dc voltage and the clock driver uses vox as its power supply. in the event where secfb drops below its feedback threshold, an ultrasonic pulse will occur to refresh the charge pump driven by lgatex. if there an overload on the charge pump in which secfb can not reach more than its feedback threshold, the controller will enter ultrasonic mode. special care should be taken to ensure that enough normal ripple voltage is present on each cycle to prevent charge pump shutdown. the robustness of the charge pump can be increased by reducing the charge pump decoupling capacitor and placing a small ceramic capacitor, c p (47pf to 220pf), in parallel with the upper leg of the secfb resistor feedback network, r cp1 , as shown below in figure 1 . secfb up1590q voutx r cp1 charge pump lgatex c1 c2 c3 c4 c p r cp2 figure 1. functional description upi confidential up1590 10 up1590-ds-p0200, oct. 2013 www.upi-semi.com (note 1) supply input voltage, vin ------------------------------------------------------------------------------------------ -0.3v to +30v bootx to phasex -------------------------------------------------------------------------------------------------------- -0.3 v to +6v phasex to gnd dc ------------------------------------------------------------------------------------------------------------------------- -0.3v to +30v < 200ns -------------------------------------------------------------------------------------------------------------------- -5v to +38v ugatex to phasex dc---------------------------------------------------------------------------------------------------------------------- -0.3v to +6v <200ns ---------------------------------------------------------------------------------------------------------------- -5v to +7v lgatex to gnd dc ------------------------------------------------------------------------------------------------------------------------- -0.3v to +6v < 200ns ---------------------------------------------------------------------------------------------------------------- -2v to +7v other pins to gnd ------------------------------------------------------------------------------------------------------------- - -0.3v to +6v storage temperature range ----------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature ---------------------------------------------------------------------------------------------------------- ------- 150 o c lead temperature range(soldering 10se c) ----------------------------------------------------------------------------------------- 260 o c esd rating (note 2) hbm (human body mode) ---------------------------------------------------------------------------------------------------- 2k v mm (machine mode) ------------------------------------------------------------------------------------------------------------ 200v package thermal resistance (note 3) wqfn3x3 - 20l ja --------------------------------------------------------------------------------------------------------- 68 c/w wqfn3x3 - 20l jc ----------------------------------------------------------------------------------------------------------- 6 c/w power dissipation, p d @ ta = 25 c wqfn3x3 - 20l ----------------------------------------------------------------------------------------------------------------- --- 1.47w (note 4) operating junction temperature ra nge --------------------------------------------------------------------------------- -40 c to +125 c operating ambient temperature ra nge ---------------------------------------------------------------------------------- -40 c to +85 c supply input voltage, vin -------------------------------------------------------------------------------------------------------- 5.5v to 26v absolute maximum rating thermal information recommended operation conditions note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. upi confidential up1590 11 up1590-ds-p0200, oct. 2013 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tnerrucylppus tesernorewop ni vv rop gnisi r- -1 . 55 .5 v gnilla f5 . 3- -5 .4 tnerrucylppus ni vi niv v,daolon 1bfv v= 2bfv v50.2 =- -5 5. 00 1. 1a m tnerrucybdnats ni vi ybtsniv v,daolon 1pirtne v= 2pirtne v5 =- -0 5 20 5 3a u tnerrucnwodtuhs ni vi ds v,daolon 0ne v0 =- -0 20 4a u tuptuo egatlovnoitaluger bf vv xbfv noitarepo mc c- -2- - v noitarepo ms p8 9. 16 00. 23 0.2 egnaregatlovtuptuo 2- -5 . 5v tnerrucegrahcsidxtuo vi ghcsid v xpirtne v,v5= xtuo v5.0 =- -3- -a m egatlov bfce sv bfces ylnoq0951p u2 9. 128 0. 2v emitno emit-n ot no v ni r,v02= not k65= v, 1esahp v5 =- -0 4 6- - sn v ni r,v02= not k65= v, 2esahp v3 =- -0 3 3- - emit-no mumini mt nimno - -0 8- -s n emit-ffo mumini mt nimffo - -- -0 0 4s n ycneuqerf f 1ws v 1tuo ycneuqerfnoitarep o0 0 2- -0 04 zhk f 2ws v 2tuo ycneuqerfnoitarep o3 3 2- -6 64 ycneuqerf ms uf msu msunignitarepospm s5 2- -- -z hk trats-tfos emitsslanretn it ss trats-tfoslanretn i- -2- -s m tuptuo 5odl egatlovtuptuo 5od lv 5odl v 1pyb i,v0= 5odl am001 <8 . 452 .5 v v 1pyb i,v0= 5odl ,am001< v62 upi confidential up1590 15 up1590-ds-p0200, oct. 2013 www.upi-semi.com 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 6 8 10 12 14 16 18 20 22 24 26 i out = 0a i out = 6a 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 v in = 8v v in = 20v v in = 12v 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 6 8 10 12 14 16 18 20 22 24 26 i out = 0a i out = 6a 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 v in = 8v v in = 20v v in = 12v vo1 efficiency output current (a) efficiency (%) vo2 efficiency output current (a) efficiency (%) typical operation characteristics vo2 load regulation output current (a) output voltage (v) vo1 line regulation input voltage (v) output voltage (v) vo1 load regulation output current (a) output voltage (v) vo2 line regulation input voltage (v) output voltage (v) upi confidential up1590 16 up1590-ds-p0200, oct. 2013 www.upi-semi.com application information output inductor selection the inductor plays an important role in step-down converters because it stores the energy from the input power rail and then releases the energy to the load. from the viewpoint of efficiency, the dc resistance (dcr) of the inductor should be as small as possible to minimize the conduction loss. in addition, the inductor covers a significant proportion of the board space, so its size is also important. low profile inductors can save board space especially when the height has a limitation. however, low dcr and low profile inductors are usually cost ineffective. additionally, larger inductance results in lower ripple current, which translates into the lower power loss. however, the inductor current rising time increases with inductance value. this means the transient response will be slower. therefore, the inductor design is a trade-off between performance, size and cost. in general, the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as shown in the following equation: () ) max ( load outx in on i lir v v t l = where lir is the ratio of the peak to peak ripple current to the average inductor current. find a low loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice because powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): ) max ( load ) max ( load peak i 2 lir i i = + the calculation above shall serve as a general reference. to further improve the transient response, the output inductance can be reduced even further. this needs to be considered along with the selection of the output capacitor. output capacitor selection the capacitor value and esr determine the amount of output voltage ripple and load transient response. thus, the capacitor value must be greater than the largest value calculated from below equations: outx out 2 load soar v c 2 l i v = ? ?? ? ? ?? ? + = sw out ) max ( load pp f c 8 1 esr i lir v where v soar are the allowable amount of undershoot voltage and overshoot voltage in the load transient, v p-p is the output ripple voltage. mosfet selection the majority of power loss in the step-down power converter is the loss in the power mosfets. for low voltage high current applications, the duty cycle of the upper mosfet is small. therefore, the switching loss of the upper mosfet is of concern. power mosfets with lower total gate charge are preferred in such kind of application. however, the small duty cycle means the lower mosfet is on for most of the switching cycle. therefore, the conduction loss tends to dominate the total power loss of the converter. to improve the overall efficiency, mosfets with low r ds(on) are preferred in the circuit design. in some cases, more than one mosfet are connected in parallel to further decrease the on-state resistance. however, this depends on the mosfet driver capability and the budget. layout considerations layout is very important in high frequency switching converter designs, the pcb could radiate excessive noise and contribute to the converter instability with improper layout. certain points must be considered before starting a layout. ? ? ? ? ? place the filter capacitor close to the ic. ? ? ? ? ? keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high voltage switching node. ? ? ? ? ? connections from the drivers to the respective gate of the upper or the lower mosfet should be as short as possible to reduce stray inductance. ? ? ? ? ? all sensitive analog traces and components such as vfbx, gnd, entripx and pok should be placed away from high voltage switching nodes such as phasex, lgatex, ugatex, or bootx nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ? ? ? ? ? place the ground terminals of vin capacitor(s), voutx capacitor(s), and source of lower mosfets as close as possible. the pcb trace defined as phasex node, which connects to source of upper mosfet, drain of lower mosfet and high voltage side of the inductor, should be as short and wide as possible. upi confidential up1590 17 up1590-ds-p0200, oct. 2013 www.upi-semi.com package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. wqfn3x3-20l 2.90 - 3.10 pin 1 mark bottom view - exposed pad 1.40-1.80 0.15 - 0.25 1.40 - 1.80 0.30 - 0.50 2.90 - 3.10 0.00 - 0.05 0.70 - 0.80 0.20 ref upi confidential up1590 18 up1590-ds-p0200, oct. 2013 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. however, no res ponsibility is assumed by upi or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2011, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064 |
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